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A. Ahmad
A. Host-Madsen
J. Giglmayr
Kwang Mong Sim
L. Ludman
R. S. Ramakrishna
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S.-H. Kim, E.-J. Oh, H.-Y. Choi, D.-I. Lee
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Synthesis for Testability Using Undefined States on State Transition Graph
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Synthesis for Testability Using Undefined States on State Transition Graph
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±è¼öÇö,¿ÀÀºÁ¤,ÃÖÈ£¿ë,À̵¿ÀÍ, "Synthesis for Testability Using Undefined States on State Transition Graph,"
Proc. of International Technical Conference on Circuits,Systems,Computers and Comm.
, pp. 430-433, 2001.
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 ±è¼öÇö-Synthesis for Testability 430.pdf (587KB)
  
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Acknowledgment
Keywords
synthesis-for-testability, undefined states, legal states, illegal states, strongly-connected graph
Abstract
In this paper, we propose an approach for synthesis for testability using undefined states on State Transition Graph (STG) in order to reduce the number of redundant faults. In case of an incompletely-specified STG, undefined states and state transitions are added to the STG to be strongly connected, and in case of completely-specified STG, transitions of specific defined states with many incoming edges are modified. Experimental results with ISCAS 93 benchmarks show that fault coverages of stuck-at-faults for synthesized gate-level circuits by our modified STGs are much higher than those of previous approach[4].
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